The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2023
Filed:
Mar. 25, 2021
Applicant:
Nxp B.v., Eindhoven, NL;
Inventors:
Mark Douglas Hall, Austin, TX (US);
Tushar Praful Merchant, Austin, TX (US);
Anirban Roy, Austin, TX (US);
Assignee:
NXP B.V., Eindhoven, NL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 27/0922 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01);
Abstract
A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (--) which are separated from one another by a barrier oxide layer () and which are separately processed to form bottom gate electrodes having a first gate structure (A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (A-B) in the top Si/SiGe superlattice structures.