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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11775805 B1

PDFFull Text
Date of Patent:
Oct. 03, 2023

Filed:

Jun. 29, 2018

Deep neural network architecture using piecewise linear approximation

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kamlesh Pillai, Bangalore, IN;

Gurpreet S. Kalsi, Bangalore, IN;

Amit Mishra, Bangalore, IN;

Assignee:

Intel Coroporation, Santa Clara, CA (US);

Attorney:

Akona IP

Primary Examiner:

Kamran Afshar

Assistant Examiner:

Randall K Baldwin

Int. Cl.
CPC ...
G06N 3/048 (2023.01); G06F 17/11 (2006.01); G06N 3/063 (2023.01); G06F 7/499 (2006.01); G06F 7/556 (2006.01); G06N 3/084 (2023.01); G06F 17/17 (2006.01); G06N 3/045 (2023.01); G06N 3/044 (2023.01);
U.S. Cl.
CPC ...
G06N 3/048 (2023.01); G06F 7/49957 (2013.01); G06F 7/556 (2013.01); G06F 17/11 (2013.01); G06F 17/17 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G06N 3/084 (2013.01); G06N 3/044 (2023.01);
Abstract

A log circuit for piecewise linear approximation is disclosed. The log circuit identifies an input associated with a logarithm operation to be performed using piecewise linear approximation. The log circuit then identifies a range that the input falls within from various ranges associated with piecewise linear approximation (PLA) equations for the logarithm operation, where the identified range corresponds to one of the PLA equations. The log circuit computes a result of the corresponding PLA equation based on the respective operands of the equation. The log circuit then returns an output associated with the logarithm operation, which is based at least partially on the result of the PLA equation.

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