The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2023
Filed:
Apr. 06, 2021
Applicant:
Winbond Electronics Corp., Taichung, TW;
Inventors:
Sho Okabe, Kanagawa, JP;
Makoto Senoo, Kanagawa, JP;
Assignee:
Winbond Electronics Corp., Taichung, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G06F 12/0891 (2016.01); G06F 11/10 (2006.01); G06F 12/0879 (2016.01); G06F 12/0882 (2016.01); G11C 16/24 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 11/1068 (2013.01); G06F 12/0246 (2013.01); G06F 12/0879 (2013.01); G06F 12/0882 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01);
Abstract
A semiconductor apparatus implementing a high speed data output and compensating a resetting of a latch circuit is provided. A readout method of a NAND type flash memory includes: a pre-charging step performing a pre-charging on a bit line and a NAND string connected to the bit line through a sense node (SNS); a resetting step performing a resetting on the latch circuit after the pre-charging; and a discharging step performing a discharging on the NAND string after the resetting.