The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

Feb. 23, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Manoj R. Sastry, Portland, OR (US);

Alpa Narendra Trivedi, Hillsboro, OR (US);

Men Long, Fullerton, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/72 (2013.01); G09C 1/00 (2006.01); G06F 21/85 (2013.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01);
U.S. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 21/85 (2013.01); G09C 1/00 (2013.01); H04L 9/0643 (2013.01); H04L 9/0897 (2013.01); G06F 2207/7219 (2013.01); G06F 2211/008 (2013.01); G06F 2213/0038 (2013.01); H04L 2209/76 (2013.01);
Abstract

Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.


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