The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

Sep. 11, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Samuel E. Bradshaw, Sacramento, CA (US);

Justin Eno, El Dorado Hills, CA (US);

Assignee:

MICRON TECHNOLOGY, INC., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 3/0616 (2013.01); G06F 3/0647 (2013.01); G06F 3/0679 (2013.01); G06F 12/1009 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7211 (2013.01);
Abstract

A wear-leveling process for a memory subsystem selects a source chunk to be removed from a usable address space of the memory subsystem to distribute wear across all available chunks in the memory subsystem. The memory subsystem has a plurality of non-volatile memory components. The plurality of non-volatile memory components includes a plurality of chunks including at least one chunk in an unusable address space of the memory subsystem. The wear-leveling process copies valid data of the source chunk to a destination chunk in the unusable address space of the memory subsystem and assigns the destination chunk to a location in the usable address space of the memory subsystem occupied by the source chunk.


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