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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11768733 B1

PDFFull Text
Date of Patent:
Sep. 26, 2023

Filed:

Feb. 14, 2022

Error correcting codes for multi-master memory controller

Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Abhijeet Ashok Chachad, Plano, TX (US);

David Matthew Thompson, Dallas, TX (US);

Son Hung Tran, Murphy, TX (US);

Assignee:

Texas Instruments Incorporated, Dallas, TX (US);

Attorneys:

Michael T. Gabrik

Frank D. Cimino

Primary Examiner:

Guy J Lamarre

Int. Cl.
CPC ...
H03M 13/27 (2006.01); H04L 27/34 (2006.01); H04L 1/00 (2006.01); H03M 13/25 (2006.01); G06F 11/10 (2006.01); G06N 3/045 (2023.01); H03M 13/15 (2006.01); G06F 9/38 (2018.01); G06F 12/0879 (2016.01); G06F 9/30 (2018.01); G06F 9/46 (2006.01); G06F 9/448 (2018.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06F 12/0811 (2016.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/106 (2013.01); G06F 9/30047 (2013.01); G06F 9/30101 (2013.01); G06F 9/3867 (2013.01); G06F 9/4498 (2018.02); G06F 9/467 (2013.01); G06F 9/4812 (2013.01); G06F 9/52 (2013.01); G06F 11/1068 (2013.01); G06F 12/0811 (2013.01); G06F 12/0879 (2013.01); G06F 13/1668 (2013.01); H03M 13/1575 (2013.01); G06F 2212/608 (2013.01);
Abstract

An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.

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