The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

May. 05, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Rajesh Sundaram, Folsom, CA (US);

Derchang Kau, Cupertino, CA (US);

Owen W. Jungroth, Sonora, CA (US);

Daniel Chu, Folsom, CA (US);

Raymond W. Zeng, Sunnyvale, CA (US);

Shekoufeh Qawami, El Dorado Hills, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 8/12 (2006.01); G11C 7/10 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0644 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 3/0688 (2013.01); G11C 7/1042 (2013.01); G11C 7/1045 (2013.01); G11C 8/12 (2013.01); G11C 16/08 (2013.01);
Abstract

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.


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