The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2023
Filed:
Oct. 12, 2021
Applicant:
Winbond Electronics Corp., Taichung, TW;
Inventors:
Assignee:
Winbond Electronics Corp., Taichung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); G11C 11/408 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H10B 12/482 (2023.02); G11C 5/063 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4097 (2013.01); H10B 12/03 (2023.02); H10B 12/34 (2023.02); H10B 12/485 (2023.02); H10B 12/488 (2023.02);
Abstract
A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.