The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2023
Filed:
Sep. 28, 2021
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Arvind Kumar, Austin, TX (US);
Mahendra Pakala, Saratoga, CA (US);
Ellie Y. Yieh, San Jose, CA (US);
John Tolle, Gilbert, AZ (US);
Thomas Kirschenheiter, Tempe, AZ (US);
Anchuan Wang, San Jose, CA (US);
Zihui Li, Sunnyvale, CA (US);
Assignee:
Applied Materials, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 21/0262 (2013.01); H01L 21/02579 (2013.01); H01L 21/30604 (2013.01); H01L 29/0665 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01); H10B 12/05 (2023.02); H10B 12/30 (2023.02);
Abstract
Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.