The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Jul. 26, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Qisong Lin, El Dorado Hills, CA (US);

Shuai Xu, Santa Clara, CA (US);

Jonathan S. Parry, Boise, ID (US);

Jeremy Binfet, Boise, ID (US);

Michele Piccardi, Cupertino, CA (US);

Qing Liang, Shanghai, CN;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/30 (2006.01); G06F 3/06 (2006.01); G06F 12/0875 (2016.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/30 (2013.01); G06F 3/0625 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01); G06F 12/0875 (2013.01); G11C 16/10 (2013.01); G06F 2212/603 (2013.01); G11C 16/0483 (2013.01);
Abstract

Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.


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