The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Dec. 13, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kuiyon Mun, Busan, KR;

Beomkyu Shin, Seongnam-si, KR;

Jaeyong Jeong, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 8/06 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 7/106 (2013.01); G11C 7/1066 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 8/06 (2013.01);
Abstract

A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.


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