The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2023
Filed:
Mar. 23, 2022
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Arun Babu Pallerla, San Diego, CA (US);
Anil Chowdary Kota, San Diego, CA (US);
Changho Jung, San Diego, CA (US);
Assignee:
QUALCOMM INCORPORATED, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G11C 7/08 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/08 (2013.01); G11C 7/1009 (2013.01); G11C 7/1012 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01);
Abstract
A memory is provided with a clock circuit configured to simultaneously assert a write multiplexer clock signal and a read multiplexer clock signal during a scan mode of operation. In the scan mode of operation, a scan in signal routes through a write multiplexer to a first bit line while the write multiplexer clock signal is asserted. Similarly, the scan in signal routes from the first bit line through a read multiplexer while the read multiplexer clock signal is asserted.