The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Jul. 28, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jung-Piao Chiu, Kaohsiung, TW;

Yu-Sheng Chen, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 25/065 (2023.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); H01L 25/0652 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); H10B 63/84 (2023.02); H10N 70/011 (2023.02); H10N 70/821 (2023.02);
Abstract

A memory device includes transistors and a memory cell array disposed over and electrically coupled to the transistors. The memory cell array includes word lines, bit line columns, and data storage layers interposed between the word lines and the bit line columns. A first portion of the word lines on odd-numbered tiers of the memory cell array is oriented in a first direction, and a second portion of the word lines on even-numbered tiers of the memory cell array is oriented in a second direction that is angularly offset from the first direction. The bit line columns pass through the odd-numbered tiers and the even-numbered tiers, and each of the bit line columns is encircled by one of the data storage layers. A semiconductor die and a manufacturing method of a semiconductor structure are also provided.


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