The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Jul. 30, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ajit Singh, Bangalore, IN;

Bharat Daga, Bangalore, IN;

Michael Behar, Israel, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/08 (2023.01); G06F 13/10 (2006.01); G06N 3/04 (2023.01); G06N 5/046 (2023.01); G06T 15/20 (2011.01); G06F 17/16 (2006.01); G06F 13/28 (2006.01); G06N 20/00 (2019.01); G06T 9/00 (2006.01);
U.S. Cl.
CPC ...
G06N 5/046 (2013.01); G06F 13/10 (2013.01); G06F 13/28 (2013.01); G06F 17/16 (2013.01); G06N 3/04 (2013.01); G06N 3/08 (2013.01); G06N 20/00 (2019.01); G06T 9/002 (2013.01); G06T 15/205 (2013.01);
Abstract

Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.


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