The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Nov. 23, 2020
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Amyn A. Poonawala, Santa Clara, CA (US);

Jason Jiale Shu, San Jose, CA (US);

Thomas Christopher Cecil, Menlo Park, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/20 (2006.01); G06F 30/398 (2020.01); G03F 1/70 (2012.01); G06F 30/33 (2020.01); G06F 30/39 (2020.01); G03F 1/36 (2012.01); G03F 1/76 (2012.01); G06N 3/08 (2023.01);
U.S. Cl.
CPC ...
G03F 1/70 (2013.01); G03F 1/36 (2013.01); G03F 1/76 (2013.01); G06F 30/33 (2020.01); G06F 30/39 (2020.01); G06N 3/08 (2013.01);
Abstract

Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. A plurality of training masks, for a machine learning (ML) model, are generated by synthesizing one or more polygons, relating to a design pattern for the semiconductor device, using Inverse Lithography Technology (ILT) (). The ML model is trained using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs (). The trained ML model is configured to synthesize one or more masks, for use in manufacturing the semiconductor device, based on the design pattern ().


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