The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Mar. 11, 2022
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Vineeth Anavangot, Bangalore, IN;

Riju Biswas, Noida, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H03L 7/18 (2006.01); H03L 7/099 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1806 (2013.01); H03L 7/099 (2013.01); H04L 7/033 (2013.01);
Abstract

In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency. The circuit includes a comparator to provide a series of bits based on the reference input signal and a comparator reference signal, and proportional accumulator circuits to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit. The circuit includes shift registers to shift the respective bit of the series to provide a shifted bit during the respective different time intervals, and a cancellation circuit to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit.


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