The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

May. 03, 2022
Applicant:

Hangzhou Silicon-magic Semiconductor Technology Co., Ltd., Hangzhou, CN;

Inventors:

Bing Wu, Zhejiang, CN;

Chien Ling Chan, Zhejiang, CN;

Liang Tong, Zhejiang, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 21/3213 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/308 (2013.01); H01L 21/32139 (2013.01); H01L 29/0653 (2013.01); H01L 29/0865 (2013.01); H01L 29/0882 (2013.01); H01L 29/1087 (2013.01); H01L 29/1095 (2013.01); H01L 29/401 (2013.01); H01L 29/402 (2013.01); H01L 29/4175 (2013.01); H01L 29/41766 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/7835 (2013.01);
Abstract

An LDMOS transistor and a method for manufacturing the same are provided. The method includes: forming an epitaxial layer on a substrate, forming a gate structure on an upper surface of the epitaxial layer, forming a body region and a drift region in the epitaxial layer, forming a source region in the body region, forming a first insulating layer on the gate structure and an upper surface of the epitaxial layer and, forming a shield conductor layer on the first insulating layer, forming a second insulating layer covering the shield conductor layer, forming a first conductive path, to connect the source region with the substrate, and forming a drain region in the drift region. By forming the first conductive path which connects the source region with the substrate, the size of the LDMOS transistor and the resistance can be reduced.


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