The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Dec. 03, 2020
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Jenn-Gwo Hwu, Taipei, TW;

Chien-Shun Liao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/51 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/06 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7391 (2013.01); H01L 21/28088 (2013.01); H01L 29/0649 (2013.01); H01L 29/0684 (2013.01); H01L 29/423 (2013.01); H01L 29/45 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66356 (2013.01); H01L 21/26513 (2013.01);
Abstract

Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.


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