The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Jan. 25, 2022
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Wei-Yu Lin, Hsinchu, TW;

Chuan-Chieh Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/64 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 28/87 (2013.01); H01L 23/5223 (2013.01); H01L 23/642 (2013.01); H01L 28/91 (2013.01); H01L 28/92 (2013.01);
Abstract

A capacitor structure including a substrate, a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a third electrode, and a stress balance layer is provided. The substrate has trenches and a pillar portion located between two adjacent trenches. The first electrode is disposed on the substrate, on the pillar portion, and in the trenches. The first dielectric layer is disposed on the first electrode and in the trenches. The second electrode is disposed on the first dielectric layer and in the trenches. The second dielectric layer is disposed on the second electrode and in the trenches. The third electrode is disposed on the second dielectric layer and in the trenches. The third electrode has a groove, and the groove is located in the trench. The stress balance layer is disposed in the groove.


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