The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Mar. 08, 2021
Applicant:

Credo Technology Group Limited, Grand Cayman, KY;

Inventors:

Mengying Ma, Shanghai, CN;

Xike Liu, Shanghai, CN;

Xiangxiang Ye, Shanghai, CN;

Xin Wang, Shanghai, CN;

Assignee:

Credo Technology Group Limited, Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H03H 11/28 (2006.01); H03M 9/00 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 23/49838 (2013.01); H01L 24/81 (2013.01); H03H 11/28 (2013.01); H03M 9/00 (2013.01); H01L 2223/6616 (2013.01); H01L 2224/81908 (2013.01); H01L 2224/81986 (2013.01); H01L 2924/30105 (2013.01); H01L 2924/30111 (2013.01);
Abstract

An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance.


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