The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Nov. 23, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Vikram Suresh, Portland, OR (US);

Sanu Mathew, Portland, OR (US);

Manoj Sastry, Portland, OR (US);

Santosh Ghosh, Hillsboro, OR (US);

Raghavan Kumar, Hillsboro, OR (US);

Rafael Misoczki, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/40 (2022.01); H04L 9/32 (2006.01); H04L 9/06 (2006.01); G06F 9/38 (2018.01); H04L 9/08 (2006.01); H04L 9/00 (2022.01);
U.S. Cl.
CPC ...
H04L 9/3247 (2013.01); G06F 9/3877 (2013.01); H04L 9/0643 (2013.01); H04L 9/0861 (2013.01); H04L 9/50 (2022.05);
Abstract

In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.


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