The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Mar. 01, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Xue Bai Pitner, San Jose, CA (US);

Raghuveer S. Makala, Campbell, CA (US);

Fei Zhou, San Jose, CA (US);

Senaka Kanakamedala, San Jose, CA (US);

Ramy Nashed Bassely Said, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H10B 51/20 (2023.01);
U.S. Cl.
CPC ...
H01L 29/42364 (2013.01); H01L 29/40111 (2019.08); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/7827 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 51/20 (2023.02);
Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and memory opening fill structures located in the memory opening and including a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner. A subset of the insulating layers a lower insulating sublayer, an upper insulating sublayer overlying the lower insulating sublayer, and a center insulating sublayer located between and in contact with the lower insulating sublayer and the upper insulating sublayer.


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