The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Aug. 17, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ravi L. Sahita, Portland, OR (US);

Tin-Cheung Kung, Folsom, CA (US);

Vedvyas Shanbhogue, Austin, TX (US);

Barry E. Huntley, Hillsboro, OR (US);

Arie Aharon, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 9/50 (2006.01); H04L 9/06 (2006.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 9/455 (2013.01); G06F 9/45533 (2013.01); G06F 9/50 (2013.01); G06F 9/5005 (2013.01); G06F 9/5011 (2013.01); G06F 9/5016 (2013.01); G06F 9/5022 (2013.01); G06F 9/5061 (2013.01); H04L 9/06 (2013.01); H04L 9/0618 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45566 (2013.01); G06F 2009/45575 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45587 (2013.01);
Abstract

Implementations describe a computing system that implements a plurality of virtual machines inside a trust domain (TD), enabled via a secure arbitration mode (SEAM) of the processor. A processor includes one or more registers to store a SEAM range of memory, a TD key identifier of a TD private encryption key. The processor is capable of initializing a trust domain resource manager (TDRM) to manage the TD, and a virtual machine monitor within the TD to manage the plurality of virtual machines therein. The processor is further capable of exclusively associating a plurality of memory pages with the TD, wherein the plurality of memory pages associated with the TD is encrypted with a TD private encryption key inaccessible to the TDRM. The processor is further capable of using the SEAM range of memory, inaccessible to the TDRM, to provide isolation between the TDRM and the plurality of virtual machines.


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