The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Sep. 28, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Xiangxin Rui, Campbell, CA (US);

Lai Zhao, Campbell, CA (US);

Jrjyan Jerry Chen, Campbell, CA (US);

Soo Young Choi, Fremont, CA (US);

Yujia Zhai, Fremont, CA (US);

Assignee:

APPLIED MATERIAL, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 49/02 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1255 (2013.01); H01L 27/1222 (2013.01); H01L 27/1237 (2013.01); H01L 27/1248 (2013.01); H01L 27/1259 (2013.01); H01L 27/1262 (2013.01); H01L 28/55 (2013.01); H01L 29/4908 (2013.01); H01L 29/78675 (2013.01);
Abstract

Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.


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