The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Aug. 12, 2019
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Shahram Nikoukary, Mountain View, CA (US);

Jonghyun Cho, Santa Clara, CA (US);

Nitin Juneja, Fremont, CA (US);

Ming Li, Fremont, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 23/49816 (2013.01);
Abstract

Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.


Find Patent Forward Citations

Nikoukary, Shahram. (2023). Packaged integrated device having memory buffer integrated circuit asymmetrically positioned on substrate (U.S. Patent No. 11742277). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11742277

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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