The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Nov. 07, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Timothy B. Cowles, Boise, ID (US);

George B. Raad, Boise, ID (US);

James S. Rehmeyer, Boise, ID (US);

Jonathan S. Parry, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/14 (2006.01); G11C 16/30 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); G11C 16/22 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01); G11C 11/22 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 11/165 (2013.01); G11C 11/1653 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01); G11C 11/225 (2013.01); G11C 11/2253 (2013.01); G11C 11/2275 (2013.01); G11C 11/2297 (2013.01); G11C 13/0004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0038 (2013.01); G11C 13/0059 (2013.01); G11C 13/0097 (2013.01); G11C 16/08 (2013.01); G11C 16/22 (2013.01); G11C 16/30 (2013.01); G11C 17/165 (2013.01); G11C 17/18 (2013.01);
Abstract

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.


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