The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Aug. 17, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Leon Zlotnik, Camino, CA (US);

Jeremy Anderson, Hillsboro, OR (US);

Lev Zlotnik, Holon, IL;

Daniel Ballegeer, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); H03K 3/037 (2006.01); H03K 23/54 (2006.01); H03K 19/20 (2006.01); H03K 23/00 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1605 (2013.01); G06F 13/1668 (2013.01); H03K 3/0377 (2013.01); H03K 19/20 (2013.01); H03K 23/005 (2013.01); H03K 23/542 (2013.01);
Abstract

A synchronizer that can generate pipeline (e.g., FIFO, LIFO) status in a single step without intermediate synchronization. The status can be an indicator of whether a pipeline is full, empty, almost full, or almost empty. The synchronizer (also referred to as a double-sync or ripple-based pipeline status synchronizer) can be used with any kind of clock crossing pipeline and all kinds of pointer encodings. The double-sync and ripple-based pipeline status synchronizers eliminate costly validation and semi-manual timing closure, suggests better performance and testability, and have lower area and power.


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