The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Mar. 31, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jagat Shakya, Hillsboro, OR (US);

Joseph Parks, Jr., Portland, OR (US);

Ethan Caughey, Hillsboro, OR (US);

Ashwin Ashok, Hillsboro, OR (US);

Prasanna Thiyagasundaram, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/20 (2006.01); G01R 31/28 (2006.01); G01R 1/073 (2006.01); G01R 1/04 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2891 (2013.01); G01R 1/0483 (2013.01); G01R 1/07314 (2013.01); G01R 31/2853 (2013.01); G01R 31/2886 (2013.01); G01R 31/2887 (2013.01); H01L 2924/00 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01);
Abstract

An apparatus includes an input probe configured to be placed on a first cluster of u-bumps disposed on a semiconductor die, output probes configured to be respectively placed on multiple clusters of u-bumps disposed on the semiconductor die, the multiple clusters being separately connected to the first cluster. The apparatus further includes a space transformer and printed circuit board (PCB) portion including a current source configured to supply a current to the input probe placed on the first cluster, resistors having a same resistance and being connected to ground, and tester channels at which voltages are respectively measured, the tester channels being respectively connected to ends of the output probes respectively placed on the multiple clusters and being respectively connected to the resistors. The apparatus further includes a processor configured to determine whether the input probe is properly aligned with the first cluster, based on the measured voltages.


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