The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Aug. 18, 2020
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Yen-De Lee, Taipei, TW;

Ching-Yung Wang, Taichung, TW;

Chien-Hsiang Yu, Taichung, TW;

Hung-Sheng Chen, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H10N 70/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H10N 70/063 (2023.02); H10B 63/80 (2023.02); H10N 70/066 (2023.02); H10N 70/841 (2023.02);
Abstract

A resistive random access memory structure and its manufacturing method are provided. The resistive random access memory structure includes a substrate having an array region and a peripheral region. A first low-k dielectric layer located in the peripheral region has a dielectric constant of less than 3. Memory cells are located on the substrate and in the array region. A dielectric layer covers the memory cells and fills the space between adjacent memory cells in the array region, and its material layer is different from that of the first low-k dielectric layer. First conductive plugs are located in the dielectric layer and each of them is in contact with one of the memory cells. A dummy memory cell is located at the boundary between the array region and the peripheral region, and the dummy memory cell is not in contact with any one of the first conductive plugs.


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