The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2023
Filed:
Aug. 22, 2019
Applicant:
Sri International, Menlo Park, CA (US);
Inventor:
Winston K. Chan, Princeton, NJ (US);
Assignee:
SRI International, Menlo Park, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/28 (2010.01); H01L 31/0296 (2006.01); H01L 31/109 (2006.01); H01L 31/18 (2006.01); H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
H01L 33/28 (2013.01); H01L 31/02966 (2013.01); H01L 31/109 (2013.01); H01L 31/1832 (2013.01); H01L 33/002 (2013.01); H01L 33/0087 (2013.01);
Abstract
Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.