The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Jan. 15, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Xin Miao, Slingerlands, NY (US);

Chen Zhang, Guilderland, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Wenyu Xu, Albany, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/207 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/0262 (2013.01); H01L 21/02546 (2013.01); H01L 21/30621 (2013.01); H01L 29/0657 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/207 (2013.01); H01L 29/66522 (2013.01); H01L 29/66666 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.


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