The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Jun. 29, 2022
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Tseng Hsun Liu, Taipei, TW;

Min-Hsuan Tsai, Tainan, TW;

Ke-Feng Lin, Taipei, TW;

Ming-Yen Liu, Hsinchu, TW;

Wen-Chung Chang, Hsinchu, TW;

Cherng-En Sun, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7825 (2013.01); H01L 29/1095 (2013.01); H01L 29/4236 (2013.01); H01L 29/6656 (2013.01);
Abstract

A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substrate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.


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