The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2023
Filed:
Jul. 06, 2022
Applicant:
Psemi Corporation, San Diego, CA (US);
Inventors:
Befruz Tasbas, San Diego, CA (US);
Simon Edward Willard, Irvine, CA (US);
Alain Duvallet, San Diego, CA (US);
Sinan Goktepeli, Austin, TX (US);
Assignee:
pSemi Corporation, San Diego, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/45 (2013.01);
Abstract
Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.