The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Jun. 02, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sangkyu Lee, Suwon-si, KR;

Jingu Kim, Suwon-si, KR;

Yongkoon Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 24/20 (2013.01); H01L 23/3121 (2013.01); H01L 24/08 (2013.01); H01L 24/13 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 2224/081 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/221 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/0651 (2013.01);
Abstract

A semiconductor package includes a support member, a semiconductor chip arranged in the support member such that a front surface and a backside surface of the semiconductor chip are exposed from a second surface of the support member and a first surface opposite to the second surface respectively, a lower redistribution wiring layer covering the second surface of the support member and including first redistribution wirings electrically connected to chip pads provided at the front surface of the semiconductor chip and vertical connection structures of the support member respectively, and an upper redistribution wiring layer covering the first surface of the support substrate, and including second redistribution wirings electrically connected to the vertical connection structures and a thermal pattern provided on the exposed backside surface of the semiconductor chip.


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