The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2023

Filed:

Jan. 29, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Murat Kerem Akarvardar, Hsinchu, TW;

Hon-Sum Philip Wong, Stanford, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5221 (2013.01); H01L 21/78 (2013.01); H01L 23/3135 (2013.01);
Abstract

A semiconductor monolithic IC includes a semiconductor substrate having a rectangular shape in plan view, multiple chiplets each comprising a circuit, wherein the multiple chiplets are disposed over the semiconductor substrate and are separated from each other by die-to-die spaces filled with a dielectric material, and a plurality of conductive connection patterns electrically connecting the multiple chiplets so that a combination of the circuit of the multiple chiplet function as one functional circuit. The chip region has a larger area than a maximum exposure area of a lithography apparatus used to fabricate the first and second circuits.


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Akarvardar, Murat. (2023). Method for low-cost, high-bandwidth monolithic system integration beyond reticle limit (U.S. Patent No. 11735515). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11735515

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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