The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2023
Filed:
Mar. 25, 2021
Applicant:
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Inventors:
You-Lung Yen, Taoyuan, TW;
Bernd Karl Appelt, Holly Springs, NC (US);
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/66 (2006.01); H01L 23/498 (2006.01); H01Q 1/22 (2006.01); H01L 23/552 (2006.01); H01L 23/14 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); H01L 21/4803 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/552 (2013.01); H01L 23/66 (2013.01); H01Q 1/2283 (2013.01); H01L 23/142 (2013.01); H01L 24/16 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/16227 (2013.01);
Abstract
A substrate structure, a package structure, and a method for manufacturing an electronic package structure provided. The substrate structure includes a dielectric layer, a trace layer, and at least one wettable flank. The dielectric layer has a first surface and a second surface opposite to the first surface. The trace layer is embedded in the dielectric layer and exposed from the first surface of the dielectric layer. The at least one wettable flank is stacked with a portion of the trace layer embedded in the dielectric layer.