The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Mar. 24, 2021
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Poren Tang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 21/768 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 21/764 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/7682 (2013.01); H01L 29/41775 (2013.01); H01L 29/4991 (2013.01); H01L 29/6653 (2013.01); H01L 29/66575 (2013.01); H01L 21/764 (2013.01); H01L 29/78 (2013.01);
Abstract

The present specification discloses a semiconductor device and a method for manufacturing same. In one implementation, the method may include: providing a semiconductor structure, wherein the semiconductor structure includes a substrate, a gate structure disposed on the substrate, initial spacer layers on side surfaces of two sides of the gate structure, and a first inter-layer dielectric layer covering the gate structure and the initial spacer layers; and the substrate includes a source and a drain respectively located on the two sides of the gate structure; etching the first inter-layer dielectric layer to form a source contact hole and a drain contact hole that expose a part of the initial spacer layer; removing the exposed part of the initial spacer layer to expose the side surface of the gate structure; forming a spacer structure layer on the exposed side surface of the gate structure; forming a source contact member and a drain contact member in the contact holes; selectively removing at least a part of the spacer structure layer to form an air gap; and forming a second inter-layer dielectric layer covering the air gap. In the present invention, an air gap spacer structure can be formed and parasitic capacitance is reduced.


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