The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2023
Filed:
Apr. 08, 2020
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Benjamin Stassen Cook, Los Gatos, CA (US);
Ralf Jakobskrueger Muenster, Saratoga, CA (US);
Sreenivasan Kalyani Koduri, Allen, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 21/288 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76898 (2013.01); H01L 23/49575 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/73 (2013.01); H01L 21/2885 (2013.01); H01L 2224/32146 (2013.01); H01L 2224/73265 (2013.01);
Abstract
In some examples, a semiconductor package comprises a semiconductor die having a first surface and a second surface opposing the first surface. The package comprises an orifice extending through a thickness of the semiconductor die from the first surface to the second surface. The package comprises a set of metallic nanowires positioned within the orifice and extending through the thickness of the semiconductor die from the first surface to the second surface.