The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

May. 28, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Mark Van Dal, Linden, BE;

Gerben Doornbos, Kessel-Lo, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/8221 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H10B 10/12 (2023.02); H10B 10/125 (2023.02);
Abstract

A fin including a bottom portion, a first sacrificial layer disposed over the bottom portion, a first semiconductor layer disposed over the first sacrificial layer, a second sacrificial layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the second sacrificial layer, is formed. The second semiconductor layer protrudes from a first insulating layer. A dummy gate is formed over the second semiconductor layer. A sidewall spacer layer is formed on side faces of the dummy gate. A first dielectric layer is formed over the dummy gate and the sidewall spacer layer. The dummy gate is removed, thereby forming a gate space. The first insulating layer is etched in the gate space, thereby exposing the first semiconductor layer and the first and second sacrificial layers. The first and second sacrificial layers are removed. A gate dielectric layer and a gate electrode layer are formed.


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