The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Aug. 14, 2022
Applicant:

Hangzhou Zhongwei Photoelectric Technology Co., Ltd., Hangzhou, CN;

Inventors:

Hong Li, Hangzhou, CN;

Hong Chen, Hangzhou, CN;

Jun Wang, Hangzhou, CN;

Jian Jing, Hangzhou, CN;

Jiangshui Zhang, Hangzhou, CN;

Guangquan Zhang, Hangzhou, CN;

You Huang, Hangzhou, CN;

Zhe Liu, Hangzhou, CN;

Yongjian Fang, Hangzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/67 (2006.01); H01L 21/677 (2006.01); H01L 21/687 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67051 (2013.01); H01L 21/0206 (2013.01); H01L 21/67706 (2013.01); H01L 21/67742 (2013.01); H01L 21/67766 (2013.01); H01L 21/68707 (2013.01);
Abstract

The present disclosure provides a device for conveying and dispersing a silicon wafer (). The device for conveying and dispersing a silicon wafer () includes: a conveying component () configured for conveying a plurality of silicon wafers (); a clamping component () disposed at two sides of the conveying component (), the clamping component () being capable of clamping and conveying the plurality of silicon wafers (); and a spraying component () disposed on the clamping component (), wherein after the plurality of silicon wafers () are conveyed to an end of the conveying component () proximal to the spraying component () via the conveying component () and the clamping component (), the spraying component () is capable of spraying water on the plurality of silicon wafers () to separate adjacent two of the plurality of silicon wafers ().


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