The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Jul. 07, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kwang-woo Lee, Hwaseong-si, KR;

Han-bin Noh, Seoul, KR;

Kyu-rie Sim, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 11/56 (2006.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 11/5678 (2013.01); G11C 13/0004 (2013.01); G11C 13/0033 (2013.01); H10B 63/80 (2023.02); H10N 70/231 (2023.02); H10N 70/882 (2023.02); G11C 2013/0092 (2013.01);
Abstract

A method of operating a resistive memory device to increase a read margin includes applying a write pulse to a memory cell such that the memory cell is programmed to a target resistance state, and applying a post-write pulse to the memory cell to increase a resistance of the memory cell that is in the target resistance state, the post-write pulse being applied as a single pulse having at least n stepped voltage levels, n being an integer equal to or more than 2, and an n-th stepped voltage level of the post-write pulse is set to be lower than a minimum threshold voltage level of the target resistance state that is changed by an (n−1)-th stepped voltage level of the post-write pulse.


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