The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Jul. 26, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shao-Huan Wang, Hsinchu, TW;

Sheng-Hsiung Chen, Hsinchu, TW;

Wen-Hao Chen, Hsinchu, TW;

Chun-Chen Chen, Hsinchu, TW;

Hung-Chih Ou, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/3312 (2020.01); G06F 30/373 (2020.01); G06F 30/33 (2020.01); G06F 30/337 (2020.01); G06F 30/398 (2020.01); H01L 23/52 (2006.01); H01L 23/522 (2006.01); G06F 111/04 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/392 (2020.01); G06F 30/33 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2119/12 (2020.01); H01L 23/5226 (2013.01);
Abstract

A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.


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