The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Jun. 09, 2022
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc Nanjing Company, Limited, Nanjing, CN;

Inventors:

Ankita Patidar, Hsinchu, TW;

Sandeep Kumar Goel, Hsinchu, TW;

Yun-Han Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/398 (2020.01); G06F 30/333 (2020.01); G06F 30/3308 (2020.01); G06F 119/18 (2020.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/398 (2020.01); G06F 30/333 (2020.01); G06F 30/3308 (2020.01); G06F 2119/02 (2020.01); G06F 2119/18 (2020.01);
Abstract

A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.


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