The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Jun. 26, 2019
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Michael Miller, Raleigh, NC (US);

Dennis Doidge, Apex, NC (US);

Collins Williams, Raleigh, NC (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0895 (2016.01); G06F 12/0804 (2016.01); G06F 12/0815 (2016.01); G06F 12/0864 (2016.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 12/0895 (2013.01); G06F 9/3816 (2013.01); G06F 12/0804 (2013.01); G06F 12/0815 (2013.01); G06F 12/0864 (2013.01);
Abstract

A device includes a cache memory and a memory controller coupled to the cache memory. The memory controller is configured to receive a first read request from a cache controller over an interconnect, the first read request comprising first tag data identifying a first cache line in the cache memory, and determine that the first read request comprises a tag read request. The memory controller is further configured to read second tag data corresponding to the tag read request from the cache memory, compare the second tag data read from the cache memory to the first tag data received from the cache controller with the first read request, and if the second tag data matches the first tag data, initiate an action with respect to the first cache line in the cache memory.


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