The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Dec. 17, 2021
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Paul Gutwin, Williston, VT (US);

Lars Liebmann, Mechanicsville, NY (US);

Daniel Chanemougame, Niskayuna, NY (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 11/402 (2006.01); G11C 11/412 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/30 (2023.02); G11C 11/4023 (2013.01); G11C 11/412 (2013.01); H10B 10/12 (2023.02); H10B 12/02 (2023.02);
Abstract

In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.


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