IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11721679 B1

PDFFull Text
Date of Patent:
Aug. 08, 2023

Filed:

Aug. 06, 2021

Semiconductor package and method of fabricating the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yanggyoo Jung, Suwon-si, KR;

Chulwoo Kim, Suwon-si, KR;

Hyo-Chang Ryu, Suwon-si, KR;

Yun Seok Choi, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-do, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Quoc D Hoang

Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 23/528 (2006.01); H01L 23/48 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 23/498 (2006.01); H01L 21/683 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3675 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/528 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 25/50 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/95001 (2013.01);
Abstract

A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

Find Patent Forward Citations

Loading…