The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

May. 20, 2022
Applicant:

Alpha and Omega Semiconductor International Lp, Toronto, CA;

Inventors:

Yan Xun Xue, Los Gatos, CA (US);

Madhur Bobde, Sunnyvale, CA (US);

Long-Ching Wang, Cupertino, CA (US);

Bo Chen, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/32 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 24/97 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 24/32 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68368 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/95001 (2013.01);
Abstract

A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.


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