The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2023
Filed:
Sep. 29, 2020
Xilinx, Inc., San Jose, CA (US);
Chi Fung Poon, Sunnyvale, CA (US);
Asma Laraba, San Jose, CA (US);
Parag Upadhyaya, Los Gatos, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.