The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Aug. 12, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Anthony D. Veches, Boise, ID (US);

Brian P. Callaway, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/4074 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1436 (2013.01);
Abstract

Methods, systems, and devices for dynamic power distribution for stacked memory are described. A stacked memory device may include switching components that support dynamic coupling between a shared power source of the memory device and circuitry associated with operating memory arrays of respective memory dies. In some examples, such techniques include coupling a power source with array circuitry based on an access activity or a degree of access activity for the array circuitry. In some examples, such techniques include isolating a power source from array circuitry based on a lack of access activity or a degree of access activity for the array circuitry. The dynamic coupling or isolation may be supported by various signaling of the memory device, such as signaling between memory dies, signaling between a memory die and a central controller, or signaling between the memory device and a host device.


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