Method of demand scrubbing by placing corrected data in memory-side cache

Abstract

Systems, apparatuses, and methods related to chiplets are described. A chiplet-based system may include a memory controller chiplet to control accesses to a storage array, and the memory controller chiplet can facilitate error correction and cache management in a manner to minimize interruptions to a sequence of data reads to write corrected data from a prior read back into the storage array. For example, a read command may be received at a memory controller device of the memory system from a requesting device. Data responsive to the read command may be obtained and determined to include a correctable error. The data may be corrected, transmitted to the requesting device and written to cache of the memory controller device with an indication that data is valid and dirty (e.g., includes an error or corrected error). The data is written back to the memory array in response to a cache eviction event.